Step-up circuits have been widely used in conventional semiconductor devices (referred to as ICs) such as EEPROM or flash memories in order to provide them with suitable power from a standardized single power source within the IC.
FIG. 1 is a schematic diagram of a conventional step-up circuit. The step-up circuit of FIG. 1 has a series of N-stage charge pump units U1–Un (referred to as units), with U1 being the first stage receiving a supply voltage and Un being the final output unit. The unit U1 of the first stage is supplied with a supply voltage Vcc (which is for example 2 V or 3 V) via a diode-connected N-type MOS (referred to as NMOS) transistor Q0. The output voltage of the unit Un is stored in a capacitor Co connected to the unit Un. This voltage (typically 10 V) is the output voltage Vout of the circuit.
Each of the units U1–Un has a similar structure, and only the unit U1 will be discussed. The unit U1 includes an NMOS transistor Q1 and a capacitor C1. The source S of the NMOS transistor Q1 is connected to the gate G thereof, thereby forming a so-called diode connection. The source S is also connected to the supply voltage Vcc via the NMOS transistor Q0. The drain D of the NMOS transistor Q1 is connected to the unit U2 of the next stage.
The capacitor C1 has one end connected to the source S of the NMOS transistor Q1 and the other end connected to a clock line of a first clock CLK1. The capacitors of odd numbered units U1, U3, . . . are connected to the clock line of the first clock CLK1, while the capacitors of even numbered units U2, U4, . . . are connected to a clock line of a second clock CLK2.
The clocks CLK1 and CLK2 constitute a two-phase clock having two opposite phases. The two phases have the same voltage amplitude which equals to, for example, the supply voltage Vcc.
In the step-up circuit shown in FIG. 1, when clocked by the clocks CLK1 and CLK2, capacitors of the respective units are charged up in turn to the supply voltage Vcc, creating the step-up voltage Vout. The resultant output voltage Vout may be supplied to an EEPROM for example.
The drain D and source S of the NMOS transistor of each unit are formed on a P-type substrate, which is grounded. The gate G of the NMOS is directly connected to the source S. In actuality, however, a threshold voltage Vth exists between the gate G and the drain D, so that the drain potential of respective units is lower than that of the sources S by the threshold voltage Vth. That is, the voltage stepped up by respective units will be at most [Vcc−Vth].
It is noted that the threshold voltage Vth of respective NMOS transistors increases with the potential difference between the source and the substrate potentials (the substrate normally grounded) due to the substrate bias effect. Consequently, a step-up voltage of a unit decreases from the first to the final stages.
For this reason, in order to obtain an appreciably high output voltage from a given supply voltage Vcc, it is necessary to implement many charge pump units connected in series. If the threshold voltage Vth is higher than the supply voltage Vcc, stepping up of voltage itself is not possible.
This problem is serious especially when the supply voltage Vcc is low. Therefore, there is a need to solve this problem for modern IC devices designed to be operable at a greatly reduced supply voltage.
A further problem pertinent to a step-up circuit concerns minimization of the circuit. Normally, the insulation layer serving as a dielectric of the capacitor used in a charge pump circuit is relatively thick to withstand a required stepped up voltage. However, since the capacitance of the capacitor decreases with the thickness of the insulation layer, the capacitor requires a larger area.
In order to reduce the areas of capacitors, thereby reducing the areas of the charge pump circuits, Japanese Patent Application Laid Open H5-28786 proposes an arrangement in which the insulation layers of low-voltage capacitors near the input end of the charge pump circuit have a reduced thickness while those of the capacitors near the terminal end of the charge pump circuit have an increased thickness to withstand a high stepped up voltage.
In this step-up circuit, however, the insulation layers are relatively thick near the terminal end of the circuit, which prevents reduction of the capacitor area, and in some cases could result in an increase of the capacitor area on a chip.
In addition, in the step-up circuit as shown in FIG. 1, capacitors C1–Cn of the respective units U1–Un have a relatively large capacitance so as to be able to provide a large current along with a required output voltage Vout. Thus, during a startup when all the units U1–Un begin to operate at substantially the same time, drawing a large current from the voltage supply, they cause a large voltage drop and instability in the supply voltage. This instability takes place every time the step-up circuit is started up and can cause errors in the operations (e.g. write and read) of a logic circuit, for example, of a semiconductor device equipped with a step-up circuit.
It is possible to avoid such instability by proving the power supply with a sufficiently large power to cope with a large current requirement at all times. However, it is impractical to do so with, for example, light-weight and/or miniaturized semiconductor devices for use in portable apparatuses.